1. Field of the Invention
This invention relates to a simulation method and apparatus for a semiconductor integrated circuit, and more particularly to a simulation method and apparatus which can simulate simultaneous operation characteristics of a semiconductor integrated circuit having a plurality of circuit blocks blocked for individual function units operate simultaneously, and make a determination of the simulation.
2. Description of the Related Art
Conventionally, in ordinary simulation for a semiconductor integrated circuit (IC), a net list which is connection information of an object circuit for designing such as a logic circuit blocked for each function unit and a test pattern which is testing information are inputted, and an output of a result of the simulation of the object circuit for designing and a designed expected value are compared with each other to determine whether or not the operation of the object circuit for designing is appropriate. Further, a delay value, a current consumption and so forth of the object circuit for designing are calculated using a library in which characteristic data of the object circuit for designing are stored to determine whether or not the specifications of the circuit are appropriate.
Further, as disclosed in Japanese Patent Laid-Open Application No. Heisei 2-280278, in simulation for an analog LSI (large scale integrated circuit), an object circuit for designing is divided into an already designed circuit portion and a newly designed circuit portion, and the already designed circuit portion is analyzed making use of characteristic data stored in a library while only the newly designed circuit portion is newly analyzed by execution of simulation to determine whether or not the specifications of the object circuit for designing are appropriate.
The conventional simulation apparatus for a semiconductor integrated circuit will be described with reference to FIG. 7. The conventional simulation apparatus includes an inputting section 1 for inputting a net list of a circuit block which is an object unit internal circuit for designing blocked for each predetermined function unit and a test pattern, a simulation section 2 for executing simulation, a determination section 3 for determining a result of simulation, an outputting section 4 for outputting a result of determination of simulation, and a library 5 in which delay times and other electric characteristic data of the circuit blocks are stored.
Subsequently, a conventional simulation method executed by the simulation apparatus of FIG. 7 will be described with reference to a flow chart of FIG. 8. If it is assumed that an object semiconductor integrated circuit for designing includes n circuit blocks, a net list of a first circuit block of the semiconductor integrated circuit and a test pattern will first be inputted to the inputting section 1 (steps P1 and P2). In response to the inputted net list and test pattern, the simulation section 2 executes predetermined simulation of a logic operation, a delay, a power consumption and so forth for the first circuit block using the data stored in the library 5 (step P3). Then, the determination section 3 compares a result of the simulation with a designed value of the first circuit block to determine whether or not the result of the simulation satisfies the specification, and outputs a result of the determination by way of the outputting section 4 (steps P4 and P5). Then at the next step P6, it is determined whether or not simulation has completed for all of the n circuit blocks, and here, since simulation has not completed for all of the n circuit blocks, the control sequence returns to step P1 to repeat the operations at steps P1 to P6 in a similar manner for the second circuit block and then for the third to n-th circuit blocks. When it is determined at step P6 that simulation has completed for the n-th circuit block, the processing is ended.
In the conventional simulation method and apparatus, however, since simulation is executed merely for each of circuit blocks constituting a semiconductor integrated circuit, a satisfactory result is not obtained in regard to an analysis for the case wherein a plurality of circuit blocks operate simultaneously. In other words, since simulation is conventionally executed for each of circuit blocks constituting a semiconductor integrated circuit, the conventional simulation method and apparatus ignores an influence of mutual intervention of the circuit blocks which is caused by impedances of power supply lines of the semiconductor integrated circuit including leads for external connection and bonding wires for internal connection, particularly inductance components which may cause a malfunction upon simultaneous operation of a plurality of circuit blocks of an actual semiconductor integrated circuit manufactured as a product. Consequently, with the conventional simulation method and apparatus, it is impossible to evaluate noise of counter-electromotive forces produced by electric currents flowing through the inductance components.